As data network speeds continue to increase to 200 Gbps, 400 Gbps, and beyond, migrating existing solutions for keeping packet, byte count, and other statistics for a collection of flows become increasingly costly in terms of materials, power, and area to implement. The ability to collect per flow statistics is critical to operating Carrier-Class networks for Service Providers. These statistics can be used for service-level agreement SLA monitoring, billing, historical trending analysis, and used as input into diagnostics/troubleshooting procedures. As our data networks evolve to support larger scale bandwidths (e.g., 10G→100G→400G, etc.), the ability for network elements to provide flow based statistics in a cost effective manner continues to be an important capability.
Large scale, high speed statistics collection is typically performed on hardware device (e.g., line cards, modules, blades, etc.) using expensive, very high speed external memories. Exemplary high speed external memories include Quad Data Rate Static random-access memory (QDRII SRAM), Reduced-latency Dynamic random access memory (RLDRAM), and the like. As speeds of line interfaces increase, counter update speeds increase accordingly, and counter widths must extend beyond 48-bits to prevent rollover. Some chipset vendors are even building a completely new type of very high speed application specific memories that have embedded counting functions in the hopes of providing speed/width/depth scale for future statistics collection architectures. In both cases, the scale of the solution relies on increasing both the frequency and depth of the specialized device. As a direct consequence, the cost of such architectures increases with each technology step required to improve these frequency and depth parameters.
Conventionally, many vendors approach the solution to hardware-based flow statistics counting in a similar way. That is, vendors consider the speed of the fastest moving counter bit, the width of the counter, and the number of flows and translate these into memory speed, memory width and memory depth. A suitable memory technology for all of these parameters is chosen, and the design implemented. However, conventional solutions with very high speed external memories are extremely expensive, require control of a significant number of pins on an integrated circuit, require significant area in the integrated circuit, and utilize extra power.